The present invention relates to a photomask fabrication method and photomask used for example in a semiconductor manufacturing process, and an exposure method utilizing that photomask.
The photomask utilized in the semiconductor manufacturing process is comprised of a light-blocking film (such as chromium film) formed in the desired pattern on a glass substrate. To manufacture the semiconductor device, a photomask pattern is made by projecting light onto a semiconductor wafer formed with the photoresist film using photolithographic technology, the pattern developed and after forming a resist pattern on the semiconductor wafer, that resist pattern is utilized as a mask for processes such as etching base films.
The photomask is produced using photolithographic equipment so photolithographic data in other words, CAD (computer aided design) data is converted into data for the photolithographic equipment, and a light-blocking film faithfully reproduced by patterning it on the glass substrate based on this data. In the photolithographic process, the semiconductor wafer is exposed to light utilizing the photomask.
However, in the photolithography process used in manufacturing semiconductors, the interference effect from light becomes very strong due to the need for the line width to form a pattern in the vicinity of the light exposure wavelength, and a large discrepancy occurs between the design pattern and the transfer pattern so that the optical proximity effect becomes a problem. The optical proximity effect appears as phenomenon such as variations in line width of separate lines and repeating lines and in contraction of the line edges, bringing problems such as poor gate line width control and shrinking of alignment margins. In the same etching process, the etching bottom line width varies due to differences in taper angle according to differences in spaces between patterns, causing the phenomenon of poor control of gate line width.
These effects cause increased variations (irregularities) in transistor characteristics, and ultimately cause a drop in production of semiconductor chips and a drop in speed performance, exerting an extremely adverse effect on design margins involving production efficiency and chip performance. These problems become of special concern in 0.8 μm generation logic chips requiring high density so that correction values dependent on each space were determined ahead of time and improving the control of gate width line 1 attempted by corrections made over the entire chip. These corrections measures are called optical proximity effect correction (OPC) or process proximity effect correction (PPC).
FIGS. 13A and 13B are drawings of each of the photomasks 31 [311, 312] after optical proximity effect correction (OPC) or process proximity effect correction (PPC) and show the resist pattern images 35 [351, 352] exposed, developed and obtained by utilizing these photomasks 31 [311, 312]. A separate line 32 consisting of a section where the mask pattern and the line L are separate; and density line 33 consisting of a section where the line L and space S are repeating; are formed on the photomasks 31 [311, 312].
When exposing and developing with the precorrection photomask 311 formed of both separate line 32 and density line 33 of the same line width Wo in FIG. 13A, the resist line width of the resist pattern 351 is thicker in the section of the separate line 36.
In contrast, in FIG. 13B when exposing and developing with the postcorrection format mask 312 having separate lines 32 formed with a narrower line width than the density line 33, the resist line width of the resist pattern 352 becomes the same line width as both the separate line 32 and the density line 33.
A correction grid is first needed in order to clarify what mask corrections are required. The correction grid shows individual units for determining correction values (so-called mask correction units). In recent years, high precision mask lithographic equipment has become capable of wafer calculations (in other words, the dimensions when projecting light for exposure onto the wafer) down to lithographic grids of 0.5 nm (individual units for lithographic equipment). The correction grids themselves are also smaller, and the correction accuracy has been improved.
However, trying to reduce the correction grid scale to zero also brings the disadvantages of a tremendous increase in the number of man-hours for fabricating correction tables and an increase in processing time needed for OPC (optical proximity effect correction), and requires establishing a correction grid while dealing with correction accuracy in the overall system. Most studies tend only deal with OPC (optical proximity effect correction) in terms of data processing and do not cover to what extent the process can be improved by OPC (optical proximity effect correction), or to what extent gate line width can be limited.
However, making the correction grid as near to zero as possible does not guarantee that correction accuracy will improve and no standards exist for establishing such correction grids. There is also the misconception that bringing the correction grid size closer to zero will improve correction accuracy somewhat. Yet such a correction grid also brings the risk of wasting many man-hours and mask fee costs. Consequently, since there is no improvement in controlling the gate line width on the wafer, the situation of a poor product yield continues for a long time. Also design work will fail to grasp the actual potential of the process and the customer cannot be provided with a satisfactory semiconductor chip.